/***************************************************************************//**
* \file cyreg_peri.h
*
* \brief
* PERI register definition header
*
* \note
* Generator version: 1.6.0.217
* Database revision: TVIIBE4M_WW2014_BTO
*
********************************************************************************
* \copyright
* Copyright 2016-2020, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/

#ifndef _CYREG_PERI_H_
#define _CYREG_PERI_H_

#include "cyip_peri_v2.h"

/**
  * \brief Peripheral group structure (PERI_GR0)
  */
#define CYREG_PERI_GR0_SL_CTL           ((volatile un_PERI_GR_SL_CTL_t*) 0x40004010UL)

/**
  * \brief Peripheral group structure (PERI_GR1)
  */
#define CYREG_PERI_GR1_SL_CTL           ((volatile un_PERI_GR_SL_CTL_t*) 0x40004030UL)

/**
  * \brief Peripheral group structure (PERI_GR2)
  */
#define CYREG_PERI_GR2_SL_CTL           ((volatile un_PERI_GR_SL_CTL_t*) 0x40004050UL)

/**
  * \brief Peripheral group structure (PERI_GR3)
  */
#define CYREG_PERI_GR3_CLOCK_CTL        ((volatile un_PERI_GR_CLOCK_CTL_t*) 0x40004060UL)
#define CYREG_PERI_GR3_SL_CTL           ((volatile un_PERI_GR_SL_CTL_t*) 0x40004070UL)

/**
  * \brief Peripheral group structure (PERI_GR5)
  */
#define CYREG_PERI_GR5_CLOCK_CTL        ((volatile un_PERI_GR_CLOCK_CTL_t*) 0x400040A0UL)
#define CYREG_PERI_GR5_SL_CTL           ((volatile un_PERI_GR_SL_CTL_t*) 0x400040B0UL)

/**
  * \brief Peripheral group structure (PERI_GR6)
  */
#define CYREG_PERI_GR6_CLOCK_CTL        ((volatile un_PERI_GR_CLOCK_CTL_t*) 0x400040C0UL)
#define CYREG_PERI_GR6_SL_CTL           ((volatile un_PERI_GR_SL_CTL_t*) 0x400040D0UL)

/**
  * \brief Peripheral group structure (PERI_GR9)
  */
#define CYREG_PERI_GR9_CLOCK_CTL        ((volatile un_PERI_GR_CLOCK_CTL_t*) 0x40004120UL)
#define CYREG_PERI_GR9_SL_CTL           ((volatile un_PERI_GR_SL_CTL_t*) 0x40004130UL)

/**
  * \brief Trigger group (PERI_TR_GR0)
  */
#define CYREG_PERI_TR_GR0_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008000UL)
#define CYREG_PERI_TR_GR0_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008004UL)
#define CYREG_PERI_TR_GR0_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008008UL)
#define CYREG_PERI_TR_GR0_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000800CUL)
#define CYREG_PERI_TR_GR0_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008010UL)
#define CYREG_PERI_TR_GR0_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008014UL)
#define CYREG_PERI_TR_GR0_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008018UL)
#define CYREG_PERI_TR_GR0_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000801CUL)

/**
  * \brief Trigger group (PERI_TR_GR1)
  */
#define CYREG_PERI_TR_GR1_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008400UL)
#define CYREG_PERI_TR_GR1_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008404UL)
#define CYREG_PERI_TR_GR1_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008408UL)
#define CYREG_PERI_TR_GR1_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000840CUL)
#define CYREG_PERI_TR_GR1_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008410UL)
#define CYREG_PERI_TR_GR1_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008414UL)
#define CYREG_PERI_TR_GR1_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008418UL)
#define CYREG_PERI_TR_GR1_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000841CUL)

/**
  * \brief Trigger group (PERI_TR_GR2)
  */
#define CYREG_PERI_TR_GR2_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008800UL)
#define CYREG_PERI_TR_GR2_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008804UL)
#define CYREG_PERI_TR_GR2_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008808UL)
#define CYREG_PERI_TR_GR2_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000880CUL)

/**
  * \brief Trigger group (PERI_TR_GR3)
  */
#define CYREG_PERI_TR_GR3_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C00UL)
#define CYREG_PERI_TR_GR3_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C04UL)
#define CYREG_PERI_TR_GR3_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C08UL)
#define CYREG_PERI_TR_GR3_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C0CUL)
#define CYREG_PERI_TR_GR3_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C10UL)
#define CYREG_PERI_TR_GR3_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C14UL)
#define CYREG_PERI_TR_GR3_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C18UL)
#define CYREG_PERI_TR_GR3_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40008C1CUL)

/**
  * \brief Trigger group (PERI_TR_GR4)
  */
#define CYREG_PERI_TR_GR4_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009000UL)
#define CYREG_PERI_TR_GR4_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009004UL)
#define CYREG_PERI_TR_GR4_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009008UL)
#define CYREG_PERI_TR_GR4_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000900CUL)
#define CYREG_PERI_TR_GR4_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009010UL)
#define CYREG_PERI_TR_GR4_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009014UL)
#define CYREG_PERI_TR_GR4_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009018UL)
#define CYREG_PERI_TR_GR4_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000901CUL)
#define CYREG_PERI_TR_GR4_TR_CTL8       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009020UL)
#define CYREG_PERI_TR_GR4_TR_CTL9       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009024UL)
#define CYREG_PERI_TR_GR4_TR_CTL10      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009028UL)
#define CYREG_PERI_TR_GR4_TR_CTL11      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000902CUL)
#define CYREG_PERI_TR_GR4_TR_CTL12      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009030UL)
#define CYREG_PERI_TR_GR4_TR_CTL13      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009034UL)
#define CYREG_PERI_TR_GR4_TR_CTL14      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009038UL)
#define CYREG_PERI_TR_GR4_TR_CTL15      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000903CUL)

/**
  * \brief Trigger group (PERI_TR_GR5)
  */
#define CYREG_PERI_TR_GR5_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009400UL)
#define CYREG_PERI_TR_GR5_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009404UL)
#define CYREG_PERI_TR_GR5_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009408UL)
#define CYREG_PERI_TR_GR5_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000940CUL)
#define CYREG_PERI_TR_GR5_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009410UL)
#define CYREG_PERI_TR_GR5_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009414UL)
#define CYREG_PERI_TR_GR5_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009418UL)
#define CYREG_PERI_TR_GR5_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000941CUL)
#define CYREG_PERI_TR_GR5_TR_CTL8       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009420UL)
#define CYREG_PERI_TR_GR5_TR_CTL9       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009424UL)
#define CYREG_PERI_TR_GR5_TR_CTL10      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009428UL)

/**
  * \brief Trigger group (PERI_TR_GR6)
  */
#define CYREG_PERI_TR_GR6_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009800UL)
#define CYREG_PERI_TR_GR6_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009804UL)
#define CYREG_PERI_TR_GR6_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009808UL)
#define CYREG_PERI_TR_GR6_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000980CUL)
#define CYREG_PERI_TR_GR6_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009810UL)
#define CYREG_PERI_TR_GR6_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009814UL)
#define CYREG_PERI_TR_GR6_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009818UL)
#define CYREG_PERI_TR_GR6_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000981CUL)
#define CYREG_PERI_TR_GR6_TR_CTL8       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009820UL)
#define CYREG_PERI_TR_GR6_TR_CTL9       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009824UL)
#define CYREG_PERI_TR_GR6_TR_CTL10      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009828UL)
#define CYREG_PERI_TR_GR6_TR_CTL11      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000982CUL)

/**
  * \brief Trigger group (PERI_TR_GR7)
  */
#define CYREG_PERI_TR_GR7_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C00UL)
#define CYREG_PERI_TR_GR7_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C04UL)
#define CYREG_PERI_TR_GR7_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C08UL)
#define CYREG_PERI_TR_GR7_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C0CUL)
#define CYREG_PERI_TR_GR7_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C10UL)
#define CYREG_PERI_TR_GR7_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C14UL)
#define CYREG_PERI_TR_GR7_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C18UL)
#define CYREG_PERI_TR_GR7_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x40009C1CUL)

/**
  * \brief Trigger group (PERI_TR_GR8)
  */
#define CYREG_PERI_TR_GR8_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A000UL)
#define CYREG_PERI_TR_GR8_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A004UL)
#define CYREG_PERI_TR_GR8_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A008UL)
#define CYREG_PERI_TR_GR8_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A00CUL)
#define CYREG_PERI_TR_GR8_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A010UL)
#define CYREG_PERI_TR_GR8_TR_CTL5       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A014UL)
#define CYREG_PERI_TR_GR8_TR_CTL6       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A018UL)
#define CYREG_PERI_TR_GR8_TR_CTL7       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A01CUL)
#define CYREG_PERI_TR_GR8_TR_CTL8       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A020UL)
#define CYREG_PERI_TR_GR8_TR_CTL9       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A024UL)

/**
  * \brief Trigger group (PERI_TR_GR9)
  */
#define CYREG_PERI_TR_GR9_TR_CTL0       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A400UL)
#define CYREG_PERI_TR_GR9_TR_CTL1       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A404UL)
#define CYREG_PERI_TR_GR9_TR_CTL2       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A408UL)
#define CYREG_PERI_TR_GR9_TR_CTL3       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A40CUL)
#define CYREG_PERI_TR_GR9_TR_CTL4       ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A410UL)

/**
  * \brief Trigger group (PERI_TR_GR10)
  */
#define CYREG_PERI_TR_GR10_TR_CTL0      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A800UL)
#define CYREG_PERI_TR_GR10_TR_CTL1      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A804UL)
#define CYREG_PERI_TR_GR10_TR_CTL2      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A808UL)
#define CYREG_PERI_TR_GR10_TR_CTL3      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A80CUL)
#define CYREG_PERI_TR_GR10_TR_CTL4      ((volatile un_PERI_TR_GR_TR_CTL_t*) 0x4000A810UL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR0)
  */
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C000UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C004UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C008UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C00CUL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL4  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C010UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL5  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C014UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL6  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C018UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL7  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C01CUL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL8  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C020UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL9  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C024UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C028UL)
#define CYREG_PERI_TR_1TO1_GR0_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C02CUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR1)
  */
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C400UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C404UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C408UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C40CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL4  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C410UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL5  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C414UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL6  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C418UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL7  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C41CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL8  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C420UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL9  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C424UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C428UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C42CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL12 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C430UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL13 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C434UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL14 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C438UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL15 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C43CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL16 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C440UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL17 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C444UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL18 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C448UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL19 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C44CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL20 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C450UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL21 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C454UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL22 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C458UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL23 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C45CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL24 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C460UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL25 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C464UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL26 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C468UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL27 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C46CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL28 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C470UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL29 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C474UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL30 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C478UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL31 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C47CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL32 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C480UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL33 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C484UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL34 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C488UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL35 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C48CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL36 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C490UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL37 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C494UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL38 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C498UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL39 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C49CUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL40 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4A0UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL41 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4A4UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL42 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4A8UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL43 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4ACUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL44 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4B0UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL45 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4B4UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL46 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4B8UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL47 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4BCUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL48 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4C0UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL49 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4C4UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL50 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4C8UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL51 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4CCUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL52 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4D0UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL53 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4D4UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL54 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4D8UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL55 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4DCUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL56 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4E0UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL57 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4E4UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL58 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4E8UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL59 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4ECUL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL60 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4F0UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL61 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4F4UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL62 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4F8UL)
#define CYREG_PERI_TR_1TO1_GR1_TR_CTL63 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C4FCUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR2)
  */
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C800UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C804UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C808UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C80CUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL4  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C810UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL5  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C814UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL6  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C818UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL7  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C81CUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL8  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C820UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL9  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C824UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C828UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C82CUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL12 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C830UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL13 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C834UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL14 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C838UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL15 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C83CUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL16 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C840UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL17 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C844UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL18 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C848UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL19 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C84CUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL20 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C850UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL21 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C854UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL22 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C858UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL23 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C85CUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL24 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C860UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL25 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C864UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL26 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C868UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL27 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C86CUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL28 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C870UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL29 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C874UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL30 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C878UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL31 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C87CUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL32 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C880UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL33 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C884UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL34 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C888UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL35 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C88CUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL36 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C890UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL37 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C894UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL38 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C898UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL39 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C89CUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL40 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8A0UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL41 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8A4UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL42 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8A8UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL43 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8ACUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL44 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8B0UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL45 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8B4UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL46 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8B8UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL47 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8BCUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL48 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8C0UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL49 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8C4UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL50 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8C8UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL51 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8CCUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL52 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8D0UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL53 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8D4UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL54 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8D8UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL55 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8DCUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL56 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8E0UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL57 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8E4UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL58 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8E8UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL59 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8ECUL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL60 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8F0UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL61 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8F4UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL62 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8F8UL)
#define CYREG_PERI_TR_1TO1_GR2_TR_CTL63 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000C8FCUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR3)
  */
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC00UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC04UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC08UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC0CUL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL4  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC10UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL5  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC14UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL6  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC18UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL7  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC1CUL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL8  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC20UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL9  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC24UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC28UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC2CUL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL12 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC30UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL13 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC34UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL14 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC38UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL15 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC3CUL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL16 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC40UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL17 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC44UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL18 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC48UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL19 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC4CUL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL20 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC50UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL21 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC54UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL22 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC58UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL23 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC5CUL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL24 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC60UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL25 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC64UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL26 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC68UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL27 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC6CUL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL28 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC70UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL29 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC74UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL30 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC78UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL31 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC7CUL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL32 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC80UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL33 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC84UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL34 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC88UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL35 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC8CUL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL36 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC90UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL37 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC94UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL38 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC98UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL39 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CC9CUL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL40 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCA0UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL41 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCA4UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL42 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCA8UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL43 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCACUL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL44 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCB0UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL45 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCB4UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL46 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCB8UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL47 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCBCUL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL48 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCC0UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL49 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCC4UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL50 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCC8UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL51 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCCCUL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL52 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCD0UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL53 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCD4UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL54 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCD8UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL55 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCDCUL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL56 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCE0UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL57 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCE4UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL58 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCE8UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL59 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCECUL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL60 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCF0UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL61 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCF4UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL62 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCF8UL)
#define CYREG_PERI_TR_1TO1_GR3_TR_CTL63 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000CCFCUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR4)
  */
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D000UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D004UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D008UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D00CUL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL4  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D010UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL5  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D014UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL6  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D018UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL7  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D01CUL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL8  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D020UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL9  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D024UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D028UL)
#define CYREG_PERI_TR_1TO1_GR4_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D02CUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR5)
  */
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D400UL)
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D404UL)
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D408UL)
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D40CUL)
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL4  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D410UL)
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL5  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D414UL)
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL6  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D418UL)
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL7  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D41CUL)
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL8  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D420UL)
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL9  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D424UL)
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D428UL)
#define CYREG_PERI_TR_1TO1_GR5_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D42CUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR6)
  */
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D800UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D804UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D808UL)
#define CYREG_PERI_TR_1TO1_GR6_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000D80CUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR7)
  */
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC00UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC04UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC08UL)
#define CYREG_PERI_TR_1TO1_GR7_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000DC0CUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR8)
  */
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E000UL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E004UL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E008UL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E00CUL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL4  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E010UL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL5  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E014UL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL6  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E018UL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL7  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E01CUL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL8  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E020UL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL9  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E024UL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL10 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E028UL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL11 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E02CUL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL12 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E030UL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL13 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E034UL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL14 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E038UL)
#define CYREG_PERI_TR_1TO1_GR8_TR_CTL15 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E03CUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR9)
  */
#define CYREG_PERI_TR_1TO1_GR9_TR_CTL0  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E400UL)
#define CYREG_PERI_TR_1TO1_GR9_TR_CTL1  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E404UL)
#define CYREG_PERI_TR_1TO1_GR9_TR_CTL2  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E408UL)
#define CYREG_PERI_TR_1TO1_GR9_TR_CTL3  ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E40CUL)

/**
  * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR10)
  */
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL0 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E800UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL1 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E804UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL2 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E808UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL3 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E80CUL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL4 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E810UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL5 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E814UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL6 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E818UL)
#define CYREG_PERI_TR_1TO1_GR10_TR_CTL7 ((volatile un_PERI_TR_1TO1_GR_TR_CTL_t*) 0x4000E81CUL)

/**
  * \brief Peripheral interconnect (PERI0)
  */
#define CYREG_PERI_TIMEOUT_CTL          ((volatile un_PERI_TIMEOUT_CTL_t*) 0x40000200UL)
#define CYREG_PERI_TR_CMD               ((volatile un_PERI_TR_CMD_t*) 0x40000220UL)
#define CYREG_PERI_DIV_CMD              ((volatile un_PERI_DIV_CMD_t*) 0x40000400UL)
#define CYREG_PERI_CLOCK_CTL0           ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C00UL)
#define CYREG_PERI_CLOCK_CTL1           ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C04UL)
#define CYREG_PERI_CLOCK_CTL2           ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C08UL)
#define CYREG_PERI_CLOCK_CTL3           ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C0CUL)
#define CYREG_PERI_CLOCK_CTL4           ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C10UL)
#define CYREG_PERI_CLOCK_CTL5           ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C14UL)
#define CYREG_PERI_CLOCK_CTL6           ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C18UL)
#define CYREG_PERI_CLOCK_CTL7           ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C1CUL)
#define CYREG_PERI_CLOCK_CTL8           ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C20UL)
#define CYREG_PERI_CLOCK_CTL9           ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C24UL)
#define CYREG_PERI_CLOCK_CTL10          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C28UL)
#define CYREG_PERI_CLOCK_CTL11          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C2CUL)
#define CYREG_PERI_CLOCK_CTL12          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C30UL)
#define CYREG_PERI_CLOCK_CTL13          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C34UL)
#define CYREG_PERI_CLOCK_CTL14          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C38UL)
#define CYREG_PERI_CLOCK_CTL15          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C3CUL)
#define CYREG_PERI_CLOCK_CTL16          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C40UL)
#define CYREG_PERI_CLOCK_CTL17          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C44UL)
#define CYREG_PERI_CLOCK_CTL18          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C48UL)
#define CYREG_PERI_CLOCK_CTL19          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C4CUL)
#define CYREG_PERI_CLOCK_CTL20          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C50UL)
#define CYREG_PERI_CLOCK_CTL21          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C54UL)
#define CYREG_PERI_CLOCK_CTL22          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C58UL)
#define CYREG_PERI_CLOCK_CTL23          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C5CUL)
#define CYREG_PERI_CLOCK_CTL24          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C60UL)
#define CYREG_PERI_CLOCK_CTL25          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C64UL)
#define CYREG_PERI_CLOCK_CTL26          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C68UL)
#define CYREG_PERI_CLOCK_CTL27          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C6CUL)
#define CYREG_PERI_CLOCK_CTL28          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C70UL)
#define CYREG_PERI_CLOCK_CTL29          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C74UL)
#define CYREG_PERI_CLOCK_CTL30          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C78UL)
#define CYREG_PERI_CLOCK_CTL31          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C7CUL)
#define CYREG_PERI_CLOCK_CTL32          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C80UL)
#define CYREG_PERI_CLOCK_CTL33          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C84UL)
#define CYREG_PERI_CLOCK_CTL34          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C88UL)
#define CYREG_PERI_CLOCK_CTL35          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C8CUL)
#define CYREG_PERI_CLOCK_CTL36          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C90UL)
#define CYREG_PERI_CLOCK_CTL37          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C94UL)
#define CYREG_PERI_CLOCK_CTL38          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C98UL)
#define CYREG_PERI_CLOCK_CTL39          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000C9CUL)
#define CYREG_PERI_CLOCK_CTL40          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CA0UL)
#define CYREG_PERI_CLOCK_CTL41          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CA4UL)
#define CYREG_PERI_CLOCK_CTL42          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CA8UL)
#define CYREG_PERI_CLOCK_CTL43          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CACUL)
#define CYREG_PERI_CLOCK_CTL44          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CB0UL)
#define CYREG_PERI_CLOCK_CTL45          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CB4UL)
#define CYREG_PERI_CLOCK_CTL46          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CB8UL)
#define CYREG_PERI_CLOCK_CTL47          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CBCUL)
#define CYREG_PERI_CLOCK_CTL48          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CC0UL)
#define CYREG_PERI_CLOCK_CTL49          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CC4UL)
#define CYREG_PERI_CLOCK_CTL50          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CC8UL)
#define CYREG_PERI_CLOCK_CTL51          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CCCUL)
#define CYREG_PERI_CLOCK_CTL52          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CD0UL)
#define CYREG_PERI_CLOCK_CTL53          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CD4UL)
#define CYREG_PERI_CLOCK_CTL54          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CD8UL)
#define CYREG_PERI_CLOCK_CTL55          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CDCUL)
#define CYREG_PERI_CLOCK_CTL56          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CE0UL)
#define CYREG_PERI_CLOCK_CTL57          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CE4UL)
#define CYREG_PERI_CLOCK_CTL58          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CE8UL)
#define CYREG_PERI_CLOCK_CTL59          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CECUL)
#define CYREG_PERI_CLOCK_CTL60          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CF0UL)
#define CYREG_PERI_CLOCK_CTL61          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CF4UL)
#define CYREG_PERI_CLOCK_CTL62          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CF8UL)
#define CYREG_PERI_CLOCK_CTL63          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000CFCUL)
#define CYREG_PERI_CLOCK_CTL64          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D00UL)
#define CYREG_PERI_CLOCK_CTL65          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D04UL)
#define CYREG_PERI_CLOCK_CTL66          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D08UL)
#define CYREG_PERI_CLOCK_CTL67          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D0CUL)
#define CYREG_PERI_CLOCK_CTL68          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D10UL)
#define CYREG_PERI_CLOCK_CTL69          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D14UL)
#define CYREG_PERI_CLOCK_CTL70          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D18UL)
#define CYREG_PERI_CLOCK_CTL71          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D1CUL)
#define CYREG_PERI_CLOCK_CTL72          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D20UL)
#define CYREG_PERI_CLOCK_CTL73          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D24UL)
#define CYREG_PERI_CLOCK_CTL74          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D28UL)
#define CYREG_PERI_CLOCK_CTL75          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D2CUL)
#define CYREG_PERI_CLOCK_CTL76          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D30UL)
#define CYREG_PERI_CLOCK_CTL77          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D34UL)
#define CYREG_PERI_CLOCK_CTL78          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D38UL)
#define CYREG_PERI_CLOCK_CTL79          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D3CUL)
#define CYREG_PERI_CLOCK_CTL80          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D40UL)
#define CYREG_PERI_CLOCK_CTL81          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D44UL)
#define CYREG_PERI_CLOCK_CTL82          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D48UL)
#define CYREG_PERI_CLOCK_CTL83          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D4CUL)
#define CYREG_PERI_CLOCK_CTL84          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D50UL)
#define CYREG_PERI_CLOCK_CTL85          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D54UL)
#define CYREG_PERI_CLOCK_CTL86          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D58UL)
#define CYREG_PERI_CLOCK_CTL87          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D5CUL)
#define CYREG_PERI_CLOCK_CTL88          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D60UL)
#define CYREG_PERI_CLOCK_CTL89          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D64UL)
#define CYREG_PERI_CLOCK_CTL90          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D68UL)
#define CYREG_PERI_CLOCK_CTL91          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D6CUL)
#define CYREG_PERI_CLOCK_CTL92          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D70UL)
#define CYREG_PERI_CLOCK_CTL93          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D74UL)
#define CYREG_PERI_CLOCK_CTL94          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D78UL)
#define CYREG_PERI_CLOCK_CTL95          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D7CUL)
#define CYREG_PERI_CLOCK_CTL96          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D80UL)
#define CYREG_PERI_CLOCK_CTL97          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D84UL)
#define CYREG_PERI_CLOCK_CTL98          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D88UL)
#define CYREG_PERI_CLOCK_CTL99          ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D8CUL)
#define CYREG_PERI_CLOCK_CTL100         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D90UL)
#define CYREG_PERI_CLOCK_CTL101         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D94UL)
#define CYREG_PERI_CLOCK_CTL102         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D98UL)
#define CYREG_PERI_CLOCK_CTL103         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000D9CUL)
#define CYREG_PERI_CLOCK_CTL104         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DA0UL)
#define CYREG_PERI_CLOCK_CTL105         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DA4UL)
#define CYREG_PERI_CLOCK_CTL106         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DA8UL)
#define CYREG_PERI_CLOCK_CTL107         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DACUL)
#define CYREG_PERI_CLOCK_CTL108         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DB0UL)
#define CYREG_PERI_CLOCK_CTL109         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DB4UL)
#define CYREG_PERI_CLOCK_CTL110         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DB8UL)
#define CYREG_PERI_CLOCK_CTL111         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DBCUL)
#define CYREG_PERI_CLOCK_CTL112         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DC0UL)
#define CYREG_PERI_CLOCK_CTL113         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DC4UL)
#define CYREG_PERI_CLOCK_CTL114         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DC8UL)
#define CYREG_PERI_CLOCK_CTL115         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DCCUL)
#define CYREG_PERI_CLOCK_CTL116         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DD0UL)
#define CYREG_PERI_CLOCK_CTL117         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DD4UL)
#define CYREG_PERI_CLOCK_CTL118         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DD8UL)
#define CYREG_PERI_CLOCK_CTL119         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DDCUL)
#define CYREG_PERI_CLOCK_CTL120         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DE0UL)
#define CYREG_PERI_CLOCK_CTL121         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DE4UL)
#define CYREG_PERI_CLOCK_CTL122         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DE8UL)
#define CYREG_PERI_CLOCK_CTL123         ((volatile un_PERI_CLOCK_CTL_t*) 0x40000DECUL)
#define CYREG_PERI_DIV_8_CTL0           ((volatile un_PERI_DIV_8_CTL_t*) 0x40001000UL)
#define CYREG_PERI_DIV_8_CTL1           ((volatile un_PERI_DIV_8_CTL_t*) 0x40001004UL)
#define CYREG_PERI_DIV_8_CTL2           ((volatile un_PERI_DIV_8_CTL_t*) 0x40001008UL)
#define CYREG_PERI_DIV_8_CTL3           ((volatile un_PERI_DIV_8_CTL_t*) 0x4000100CUL)
#define CYREG_PERI_DIV_8_CTL4           ((volatile un_PERI_DIV_8_CTL_t*) 0x40001010UL)
#define CYREG_PERI_DIV_8_CTL5           ((volatile un_PERI_DIV_8_CTL_t*) 0x40001014UL)
#define CYREG_PERI_DIV_8_CTL6           ((volatile un_PERI_DIV_8_CTL_t*) 0x40001018UL)
#define CYREG_PERI_DIV_8_CTL7           ((volatile un_PERI_DIV_8_CTL_t*) 0x4000101CUL)
#define CYREG_PERI_DIV_8_CTL8           ((volatile un_PERI_DIV_8_CTL_t*) 0x40001020UL)
#define CYREG_PERI_DIV_8_CTL9           ((volatile un_PERI_DIV_8_CTL_t*) 0x40001024UL)
#define CYREG_PERI_DIV_8_CTL10          ((volatile un_PERI_DIV_8_CTL_t*) 0x40001028UL)
#define CYREG_PERI_DIV_8_CTL11          ((volatile un_PERI_DIV_8_CTL_t*) 0x4000102CUL)
#define CYREG_PERI_DIV_8_CTL12          ((volatile un_PERI_DIV_8_CTL_t*) 0x40001030UL)
#define CYREG_PERI_DIV_8_CTL13          ((volatile un_PERI_DIV_8_CTL_t*) 0x40001034UL)
#define CYREG_PERI_DIV_8_CTL14          ((volatile un_PERI_DIV_8_CTL_t*) 0x40001038UL)
#define CYREG_PERI_DIV_8_CTL15          ((volatile un_PERI_DIV_8_CTL_t*) 0x4000103CUL)
#define CYREG_PERI_DIV_8_CTL16          ((volatile un_PERI_DIV_8_CTL_t*) 0x40001040UL)
#define CYREG_PERI_DIV_8_CTL17          ((volatile un_PERI_DIV_8_CTL_t*) 0x40001044UL)
#define CYREG_PERI_DIV_8_CTL18          ((volatile un_PERI_DIV_8_CTL_t*) 0x40001048UL)
#define CYREG_PERI_DIV_8_CTL19          ((volatile un_PERI_DIV_8_CTL_t*) 0x4000104CUL)
#define CYREG_PERI_DIV_8_CTL20          ((volatile un_PERI_DIV_8_CTL_t*) 0x40001050UL)
#define CYREG_PERI_DIV_8_CTL21          ((volatile un_PERI_DIV_8_CTL_t*) 0x40001054UL)
#define CYREG_PERI_DIV_8_CTL22          ((volatile un_PERI_DIV_8_CTL_t*) 0x40001058UL)
#define CYREG_PERI_DIV_8_CTL23          ((volatile un_PERI_DIV_8_CTL_t*) 0x4000105CUL)
#define CYREG_PERI_DIV_8_CTL24          ((volatile un_PERI_DIV_8_CTL_t*) 0x40001060UL)
#define CYREG_PERI_DIV_8_CTL25          ((volatile un_PERI_DIV_8_CTL_t*) 0x40001064UL)
#define CYREG_PERI_DIV_8_CTL26          ((volatile un_PERI_DIV_8_CTL_t*) 0x40001068UL)
#define CYREG_PERI_DIV_8_CTL27          ((volatile un_PERI_DIV_8_CTL_t*) 0x4000106CUL)
#define CYREG_PERI_DIV_8_CTL28          ((volatile un_PERI_DIV_8_CTL_t*) 0x40001070UL)
#define CYREG_PERI_DIV_8_CTL29          ((volatile un_PERI_DIV_8_CTL_t*) 0x40001074UL)
#define CYREG_PERI_DIV_8_CTL30          ((volatile un_PERI_DIV_8_CTL_t*) 0x40001078UL)
#define CYREG_PERI_DIV_8_CTL31          ((volatile un_PERI_DIV_8_CTL_t*) 0x4000107CUL)
#define CYREG_PERI_DIV_16_CTL0          ((volatile un_PERI_DIV_16_CTL_t*) 0x40001400UL)
#define CYREG_PERI_DIV_16_CTL1          ((volatile un_PERI_DIV_16_CTL_t*) 0x40001404UL)
#define CYREG_PERI_DIV_16_CTL2          ((volatile un_PERI_DIV_16_CTL_t*) 0x40001408UL)
#define CYREG_PERI_DIV_16_CTL3          ((volatile un_PERI_DIV_16_CTL_t*) 0x4000140CUL)
#define CYREG_PERI_DIV_16_CTL4          ((volatile un_PERI_DIV_16_CTL_t*) 0x40001410UL)
#define CYREG_PERI_DIV_16_CTL5          ((volatile un_PERI_DIV_16_CTL_t*) 0x40001414UL)
#define CYREG_PERI_DIV_16_CTL6          ((volatile un_PERI_DIV_16_CTL_t*) 0x40001418UL)
#define CYREG_PERI_DIV_16_CTL7          ((volatile un_PERI_DIV_16_CTL_t*) 0x4000141CUL)
#define CYREG_PERI_DIV_16_CTL8          ((volatile un_PERI_DIV_16_CTL_t*) 0x40001420UL)
#define CYREG_PERI_DIV_16_CTL9          ((volatile un_PERI_DIV_16_CTL_t*) 0x40001424UL)
#define CYREG_PERI_DIV_16_CTL10         ((volatile un_PERI_DIV_16_CTL_t*) 0x40001428UL)
#define CYREG_PERI_DIV_16_CTL11         ((volatile un_PERI_DIV_16_CTL_t*) 0x4000142CUL)
#define CYREG_PERI_DIV_16_CTL12         ((volatile un_PERI_DIV_16_CTL_t*) 0x40001430UL)
#define CYREG_PERI_DIV_16_CTL13         ((volatile un_PERI_DIV_16_CTL_t*) 0x40001434UL)
#define CYREG_PERI_DIV_16_CTL14         ((volatile un_PERI_DIV_16_CTL_t*) 0x40001438UL)
#define CYREG_PERI_DIV_16_CTL15         ((volatile un_PERI_DIV_16_CTL_t*) 0x4000143CUL)
#define CYREG_PERI_DIV_24_5_CTL0        ((volatile un_PERI_DIV_24_5_CTL_t*) 0x40001C00UL)
#define CYREG_PERI_DIV_24_5_CTL1        ((volatile un_PERI_DIV_24_5_CTL_t*) 0x40001C04UL)
#define CYREG_PERI_DIV_24_5_CTL2        ((volatile un_PERI_DIV_24_5_CTL_t*) 0x40001C08UL)
#define CYREG_PERI_DIV_24_5_CTL3        ((volatile un_PERI_DIV_24_5_CTL_t*) 0x40001C0CUL)
#define CYREG_PERI_DIV_24_5_CTL4        ((volatile un_PERI_DIV_24_5_CTL_t*) 0x40001C10UL)
#define CYREG_PERI_DIV_24_5_CTL5        ((volatile un_PERI_DIV_24_5_CTL_t*) 0x40001C14UL)
#define CYREG_PERI_DIV_24_5_CTL6        ((volatile un_PERI_DIV_24_5_CTL_t*) 0x40001C18UL)
#define CYREG_PERI_DIV_24_5_CTL7        ((volatile un_PERI_DIV_24_5_CTL_t*) 0x40001C1CUL)
#define CYREG_PERI_ECC_CTL              ((volatile un_PERI_ECC_CTL_t*) 0x40002000UL)

#endif /* _CYREG_PERI_H_ */


/* [] END OF FILE */
